No. |
Technical parameters |
Technical index |
1 |
Processor |
⑴ 2 Processors, distributed architecture for each Processor ⑵ ⑶ provide 3.6GFLOPS processing capabilities within 24M bits Signal Processor chip Memory
⑷ Integrated 14-channel DMA controller, and four 1GByte / sec full-duplex communication port LVDS Link Port |
2 |
Memory |
⑴ board memory capacity of 3 36MBit the QDR-II + SRAM; maximum data transfer speed of 600 MHz; has independent read and write ports, can read and write independently ⑵ six onboard capacity of 1GB, width of 16BIT The DDR3 Memory, can read and write data transmission at 800MHz |
3 |
FPGA |
⑴ two FPGA logic design provides 2.3 million resources, we can provide more than 20 megabytes of on-chip storage capacity, while also providing speeds of up to 500M over 2500 digital signal processing unit ⑵ rich High speed data communication interface, 24 对 RocketIO Transceiver, High speed data to meet the real-time transmission Functions |
4 |
A / D |
⑴ sampling rate of up to 2GSPS 10BIT High speed A / D converter, the channel can be flexibly configured, it can work in single-channel, low-power ⑵ 1 个 High speed AD channel, the maximum sampling rate of 2G, quantization bits 10BIT |
5 |
D / A |
⑴ onboard sampling rate of up to 4.5GSPS High speed D / A converters, 12-bit quantization to ensure high stray recovery signal ⑵ 1 个 High speed DA channel, the maximum sampling rate of 4.5G, quantization bits 12BIT |
6 |
CPCI interface |
64 66M CPCI interface, the peak transmission speed of up to 256MB / S |
7 |
Other communication port |
Within two FPGA boards have 24 pairs of RocketIO Transceiver, real-time data transmission, as well as 68 pairs of speeds of up to 1.6G of LVDS High speed differential pair |
8 |
Size |
233mm X 160mm (6U CPCI) |
9 |
Working temperature |
-40 ℃ ~ 80 ℃ |